XIO2000AZZZ

Product Summary

The XIO2000AZZZ is a single-function PCI Express to PCI translation bridge that is fully compliant to the PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0. For downstream traffic, the bridge simultaneously supports up to eight posted and four nonposted transactions for each enabled virtual channel (VC). For upstream traffic, up to six posted and four nonposted transactions are simultaneously supported for each VC. The XIO2000AZZZ interface is fully compliant to the PCI Express Base Specification, Revision 1.0a. The XIO2000AZZZ interface supports a x1 link operating at full 250 MB/s packet throughput in each direction simultaneously. Two independent VCs are supported. The second VC is optimized for isochronous traffic types and quality-of-service (QoS) applications. Also, the bridge supports the advanced error reporting capability including extended CRC (ECRC) as defined in the PCI Express Base Specification. Supplemental firmware or software is required to fully utilize both of these features.

Parametrics

XIO2000AZZZ absolute maximum ratings: (1)Supply voltage range: VDD 33: -0.5 V to 3.6 V; VDD_15: -0.5 V to 1.65 V; VCCP: -0.5 V to 5.25 V; (2)Input voltage range, VI: PCI: -0.5 V to VCCP + 0.5 V; (3)VI: PCI Express (RX): -0.6 V to 0.6 V; (4)VI: PCI Express REFCLK (single-ended): -0.5 V toVDD_33 + 0.5 V; (5)VI: PCI Express REFCLK (differential): -0.5 V toVDD_15 + 0.5 V; (6)VI: Miscellaneous 3.3-V IO: -0.5 V to VDD_33 + 0.5 V; (7)Output voltage range: VO: PCI: -0.5 V to VDD_33 + 0.5 V; (8)VO: PCI Express (TX): -0.5 V to VDD_15 + 0.5V; (9)VO: Miscellaneous 3.3-V IO: -0.5 V to VDD_33 + 0.5 V; (10)Input clamp current, (VI < 0 or VI > VDD): ±20 mA; (11)Output clamp current, (VO < 0 or VO > VDD): ±20 mA; (12)Human body model (HBM) ESD performance: 1500 V; (13)Charged device model (CDM) ESD performance: 500 V; (14)Storage temperature range, Tstg: -65℃ to 150℃.

Features

XIO2000AZZZ features: (1)Full x1 PCI Express Throughput; (2)Fully Compliant with PCI Express to; (3)PCI/PCI-X Bridge Specification,; (4)Revision 1.0; (5)Fully Compliant with PCI Express Base; (6)Specification, Revision 1.0a; (7)Fully Compliant with PCI Local Bus; (8)Specification, Revision 2.3; (9)Extended Virtual Channel (VC) Support; (10)Includes a Second VC for; (11)Quality-of-Service and Isochronous; (12)Applications; (13)PCI Express Advanced Error Reporting; (14)Capability Including ECRC Support; (15)Support for D1, D2, D3hot, and D3cold; (16)Active State Link Power Management; (17)Saves Power When Packet Activity on the; (18)PCI Express Link is Idle, Using Both L0s; (19)and L1 States; (20)Wake Event and Beacon Support; (21)Error Forwarding Including PCI Express; (22)Data Poisoning and PCI Bus Parity Errors; (23)Utilizes 100-MHz Differential PCI Express; (24)Common Reference Clock or 125-MHz; (25)Single-Ended, Reference Clock; (26)Robust Pipeline Architecture To Minimize; (27)Transaction Latency; (28)Full PCI Local Bus 66-MHz/32-Bit; (29)Throughput; (30)Support for Six Subordinate PCI Bus; (31)Masters with Internal Configurable, 2-Level; (32)Prioritization Scheme; (33)Low Power Design (<350 mW) Ensures; (34)Ease of Implementation.

Diagrams